The present invention relates to a semiconductor integrated circuit device and, particularly, to such circuit device having a test function for testing itself.
With the recent development of fine processing techniques to be used in fabricating such integrated circuit device, the integrity of semiconductor integrated circuit device has been improved more and more. With such improved integrity of semiconductor integrated circuit device, i.e., increased number of gates included therein, the test thereof becomes very difficult necessarily. The easiness of such test may depend upon easiness of detection of respective terminal failures (observability) and easiness of setting the respective terminals to desired theoretical values (controllability). It is known that the observability and the controllability of terminals behind various circuit elements of a large scale integrated circuit device are generally poor.
The scan test method has been used as a test method of semiconductor integrated circuit device, which comprises the steps of inserting register circuits having a shift register function as a whole into suitable points of a logic circuit network, connecting these registers together by means of a single shift register path, inputting, serially and externally, test pattern to set desired data in these registers when the logic circuit is tested, applying a desired logic signal to a logic circuit block of the logic circuit network connected to data output terminals of the registers to activate the network, deriving an output of the logic circuit block through parallel input terminals of the registers thereinto in parallel, providing them serially externally of a chip and observing them. With this method, the observability and the controllability of terminals behind various elements of the large scale integrated circuit device are improved.
A basic idea of scan test concerning a level sensitives synchronous circuit is disclosed in Japanese Patent Application Laid-Open No. 74668/1981.
Since semiconductor integrated circuit device to which the present invention relates includes an asymmetric sequence circuit, the content of the Laid-Open No. 74668/1981 will be referred to as an example of a conventional test method. FIG. 1 which corresponds to FIG. 2 of the Laid-Open No. 74668/1981 shows a test circuit which includes composite circuit blocks 35 and 37, an asymmetric sequence circuit block 36 including a sequence circuit, scan registers 8 to 16 each provided between adjacent ones of the circuit blocks and data selectors 26 to 34 each functioning to select either an output of a corresponding circuit block or an output of a corresponding scan register. Data input terminals of the scan registers and data input terminals D of the data selectors are supplied directly with output signals of the respective circuit blocks and test data input terminals TD of the data selectors are connected to output terminals Q of the corresponding scan registers.
A test mode selection terminal 1 is connected to mode selection terminals MS of the scan registers and the data selectors. A scan-in terminal 2 is connected to scan-in terminals SI of the scan register 8 whose output terminal Q is connected to a scan-in terminal SI of the scan register 9. A reference numeral 38 depicts a scan-out terminal.
The output terminals Q of the scan registers are connected to the scan-in terminals SI of subsequent ones of the scan registers respectively sequentially, in this manner. As a result, a shift register path is formed between the scan-in terminal 2 and the scan-out terminal 38. In FIG. 1, reference numerals 3, 4 and 5 are ordinary data input terminals and 6 is a scan clock input terminal which is connected to clock input terminals T of the scan registers.
FIG. 2 shows an example of a circuit construction of the above mentioned scan register, which includes a mode selection terminal MS, a data input terminal D, a scan-in terminal SI, a clock input terminal T, an inverter gate 51, two-input AND gates 52 and 53, a two-input OR gate 54 and a D type flipflop (D-FF) 55 of edge trigger type, Q being a data output terminal.
FIG. 3 shows an example of the data selector circuit in FIG. 1, which includes a mode selection terminal MS, a test data input terminal TD, a data input terminal D, an inverter gate 60, two-input AND gates 61 and 62 and a two-input OR gate 63, Y being an output terminal.
In a normal operation of the logic circuit network, a "H" signal is applied to the test mode selection terminal 1 (MS) and the scan clock terminal 6 (TS or T) is fixed to "L". As a result, the output terminals of the circuit blocks are connected through the data selectors to the input terminals of the corresponding circuit blocks.
That is, in FIG. 3, when "H" signal is applied to the mode selection terminal MS, the data selection circuit provides data supplied to the data input terminal D as an output at the output terminal Y through the AND gate 62 and the OR gate 63. Since the output at the output terminal Y of this circuit block is directly connected to the data input terminal D of the data selector, the output terminal Y is directly connected to the input terminal of the subsequent circuit block.
In performing a test operation, the scan mode operation and a test mode operation are expected sequentially repeatedly as follows: